AXI 4 Lite and APB Micro-Arch Design

Explore the AMBA Bus Protocol and design micro-arch on paper and code in VerilogHDL.

Eligibility

Overview

The AXI 4 Lite micro Arch course is structured to provide practical experience in designing and creating slave Micro-Architecture on piece of paper using unique approach.

• B.Tech/Diploma in EEE, ECE & EIE pursuing or completed.

• M.E/M.Tech/M.S in VLSI/Embedded/Any other specialization.

• Working Professionals.

• Any one curious!

Mode of Study

• Online Mode.

• Offline Mode (Kolkata, West Bengal)

Learning Outcomes

• Mastering the art of designing the circuit on a piece of paper in order to understand the uArch.

Key Course Features

• Demo class Available.

• Job assistance and tool support.

• Industry live projects under the supervision of 12+ experienced trainer.

• Course material, hand-outs, quizzes, assignments to assist in learning.

Course Features

• Duration - 1 Month

• Skill Level - Intermediate

• Language - English

• Assessments - Yes

• Job assistance - Available

Curriculum

• Introduction to On Chip Protocols in SoC.

• AMBA based System Overview.

• APB Protocol Overview.

• APB Signal Descriptions, APB transfers, APB State Machine.

• APB Slave Micro-architecture, (Will design it)

• AXI-Lite Protocol Overview.

• AXI-Lite Signal Descriptions, transfer.

• AXI-Lite Slave Micro-architecture, (Will design it)

• AXI4 Protocol Overview.

• AXI4 Signal Descriptions.

• AXI4 Channels, Channel Handshake.

• AXI4 addressing Options.

• AXI4 Slave Micro-architecture.

• Application of AMBA architecture inside SoC's.

Above units will be updated based on the latest industry related projects and interview questions.

Course Fee

• Contact +91 9435136663 for offers!